1. Field of the Invention
The present invention generally relates to semiconductor cells for photomask data verification and semiconductor chips and, in particular, to a semiconductor cell for photomask data verification and a semiconductor chip for verifying photomask data obtained by performing arithmetic processing on the layout data of semiconductor integrated circuits included in the semiconductor chip.
2. Description of the Related Art
As electronic equipment has become more advanced and compact in recent years, it is desired that various LSIs be more highly integrated. A semiconductor chip constituting the LSI is manufactured through multiple processes such as a photomask data generation process for generating photomask data based on a function design, a logic design, a circuit design, and a layout design; a photomask manufacturing process for manufacturing the photomask using the generated photomask data; and a semiconductor chip manufacturing process including, for example, an operation of transferring a photomask pattern onto a silicon wafer by reduced projection exposure using the manufactured photomask.
Particularly, in order to manufacture the highly-integrated semiconductor chip, it is necessary to use a photomask composed of multiple pieces of masks to form a highly-integrated pattern on a silicon wafer. Therefore, the importance of element technology for manufacturing the photomask is increased.
As a procedure for manufacturing the photomask, layout data are first generated based on a circuit design. Then, photomask data are generated based on the obtained layout data. After that, the photomask is manufactured based on the obtained photomask data.
The layout data are so-called CAD data and have layout information of circuit elements included in the semiconductor integrated circuits of a semiconductor chip. The layout data have the data of plural layers and are used for generating photomask data. As a format of the layout data, a GDS format, etc., are known.
Furthermore, the photomask data are used for generating the photomask. In order to generate the photomask data, necessary data are selected from the layout data in the GDS format, etc., or combined with each other, and then subjected to arithmetic processing. The photomask data contain mask data corresponding to the data of the respective layers of the layout data. Here, it is defined that the mask data represent data corresponding to one piece of mask in the photomask composed of multiple pieces of the masks, and the photomask data represent data corresponding to the whole photomask having the multiple pieces of masks as the data of the respective layers. As a format of the photomask data, MEBES, JEOL, etc., are known.
Note that in some cases, the photomask data are called Job Deck Files and the verification of the photomask data is called Job Deck View.
Conventionally, arithmetic processing for converting the layout data into the photomask data has been performed relatively easily, because the data of one layer among the layout data generally correspond to the mask data of one piece of mask of the photomask data. In recent years, however, the data of the plural layers are generally subjected to the arithmetic processing to generate the mask data of the one piece of mask. Therefore, the arithmetic processing becomes more complicated.
For example, in some cases, complicated arithmetic processing is performed to make uniform the arrangement of the semiconductor integrated circuits on the whole silicon wafer. Specifically, in order to maintain the flatness of the surface of a metal wiring layer included in the semiconductor integrated circuits, Patent Document 1 discloses an example of a semiconductor integrated circuit device. That is, in the semiconductor integrated circuit device, the circuit elements typically included in the semiconductor integrated circuits are provided and connected to each other. Furthermore, besides metal wirings for supplying power to the circuit elements, metal wirings called dummy metals that do not have a specific electrical function are also provided. As a result, the arrangement of the metal wirings is made uniform.
Furthermore, even if the layout data are derived from the same circuit elements, the number of the layers to be used is different depending on the presence or absence of options. Therefore, in some cases, it is necessary to perform the complicated arithmetic processing. FIG. 1 is a plan view showing the circuit configuration of a conventional semiconductor chip. As shown in FIG. 1, the semiconductor chip 110 has regions where the semiconductor integrated circuits such as a digital circuit 121, a SRAM circuit 122, an analog circuit 123, an I/O cell circuit 124, a high voltage circuit 125, and other circuits 126 are arranged. In the respective regions where the semiconductor integrated circuits are arranged, option layers peculiar to the circuits are used in some cases.
In addition, as the number of the layers increases, there is a high likelihood of the option layer being erroneously selected or the arithmetic processing being erroneously performed in the photomask data generating process in which the layout data are subjected to the arithmetic processing to obtain the photomask data. As a result, the photomask data are not be properly generated. If these improperly generated photomask data are directly used to manufacture the photomask and the semiconductor chip manufacturing process is performed, defective semiconductor chips are manufactured.
Accordingly, with respect to the obtained photomask data, it is necessary to be able to easily verify whether the layout data serving as a basis for the photomask data are properly subjected to the arithmetic processing.
In general, however, the layout data of the respective semiconductor integrated circuits of the semiconductor chip are generated by different designers. Therefore, it is time-consuming and inefficient to specify a part to be used for verifying the arithmetic processing from the photomask data of the semiconductor integrated circuits after performing the arithmetic processing for converting the layout data into the photomask data.
Accordingly, it is necessary to provide a unit for efficiently verifying the photomask data of the semiconductor integrated circuits included in the semiconductor chip.
Here, as an example of the unit for efficiently verifying the data of the layers of the layout data or the photomask data of the semiconductor chip, the layout data of the semiconductor integrated circuits included in the semiconductor chip are extracted and integrated together as a semiconductor cell different from the semiconductor integrated circuits. Specifically, a process monitor and a revision mark are used as such.
First, the process monitor is a semiconductor cell for verifying the shape of the semiconductor chip after manufacture. Referring to FIG. 2, a process monitor 130 is described. As shown in FIG. 2, the process monitor 130 is generally provided in a scribe region 131 at the periphery of a semiconductor chip 110. In the process monitor 130, shapes formed by the layers used in the semiconductor chip 110 and the circuit elements are formed. Some process monitors are used for verification at a FAB (semiconductor process factory) during a processing operation. Other process monitors are used for measuring electrical characteristics in such a manner as to bring the probe needle of a prober into contact with a pad on the wafer.
Furthermore, the revision mark is a semiconductor cell for displaying the revision history of the layers used for layout. Referring to FIGS. 3A and 3B, the revision mark is described. As shown in FIG. 3A, a semiconductor integrated circuit region 132 is provided at the central part of the semiconductor chip 110, and a revision mark 133 is provided at the peripheral part. As shown in FIG. 3B, in the revision mark 133, numbers indicating the revision history of the respective mask data constituting the photomask data of the semiconductor chip 110 are displayed in an integrated manner. For example, if the photomask data are composed of the data of four layers corresponding to four pieces of masks and the data of the first through third layers refer to version A and the data of the fourth layer refer to version B, the numbers of “LAY1A,” “LAY2A,” “LAY3A,” and “LAY4B” are displayed so as to be adjacent to each other in the data of the respective layers. Consequently, as shown in FIG. 3B, the revision mark 133, in which the numbers indicating the revision history of the data of the respective layers are displayed in an integrated manner, is provided in the photomask data.    Patent Document 1: JP-A-2007-36290
However, in order to efficiently verify an error in the results of the arithmetic processing in the photomask data obtained by performing the arithmetic processing on the layout data, if conventional methods are used to extract the layout data of the semiconductor integrated circuits included in the semiconductor chip and integrate them together as the semiconductor cell different from the semiconductor integrated circuits, the following problem arises.
When an error in the results of the arithmetic processing on the photomask data is verified using the process monitor, the process monitor is the semiconductor cell for performing the verification after the photomask is manufactured and the manufacturing process is started. Therefore, even if an error is found in the results of the arithmetic processing, the photomask has to be manufactured again, which in turn causes unnecessary operations and costs. In addition, because the process monitor is not the semiconductor cell for verifying the photomask data, the circuit elements included in the semiconductor integrated circuits of the semiconductor chip represented by the photomask data are not integrated together. Therefore, it is difficult to determine whether all the layout data of the circuit elements included in the semiconductor integrated circuits of the semiconductor chip are properly subjected to the arithmetic processing.
Furthermore, when an error in the results of the arithmetic processing on the photomask data is verified using the revision mark, the revision mark is not the semiconductor cell that reproduces the layout data of the semiconductor integrated circuits of the semiconductor chip. Therefore, it is difficult to determine whether all the layout data of the circuit elements included in the semiconductor integrated circuits of the semiconductor chip are properly subjected to the arithmetic processing.